With the frequent stories of hacking personal information of millions of customers and clients of corporations and government, data and computer security have become significant issues in computing. Organizations, such as the Trusted Computing Group, have created a number of standards for secure authentication to decrypt privileged information. HDMI and other standard communication protocols have methods for encrypting and decrypting privileged data as well, but all these solutions deal with encrypting transmitted or stored data, not the actual code and data used in the actual computer, which has left a gap where hackers may be able to get access to decrypted information within the computing systems themselves. Goto et al., in U.S. Pat. No. 7,865,733 granted Jan. 4, 2011, suggests securely decrypting data received from any external memory into the processor chip, and encrypting any data being sent off of the processor chip to external memory, and Buer, in U.S. Pat. No. 7,734,932 granted Jun. 8, 2010, suggests a solution by leaving the data and instruction encrypted in main memory, decrypting it when fetched into cache. Furthermore, while Hall, in U.S. Pat. No. 7,657,756 granted Feb. 2, 2010, suggests storing the metadata for decryption in cache, it is along with the decrypted data. These may address the problem of single-threaded, single processors residing with their own cache on secure integrated circuits (ICs), but that is not the state of all computing, e.g., cloud computing, today. Most of today's servers contain multiple ICs, each with multiple processors and multiple levels of shared cache, processing potentially different applications on virtual machines in the same chip. In this environment, one application may snoop another application within the same chip, and may do so well enough to hack it.
Convolution encrypting the source code, while helpful, may still be decrypted by detecting the frequency of the instruction codes. Other techniques such as decrypting the instruction by applying the XOR of the encrypted instruction and one or more fixed keys such as described by Henry et al., in US Patent Application Publication No. 2011/0296204, published Dec. 1, 2011, are only as good as the keys. A sufficiently robust encryption technique may be needed to be adequately tamper proof. Such a technique should be sufficiently random to be difficult to break. Butler, in U.S. Pat. No. 7,412,468 granted Aug. 12, 2008, suggested using a Multiple Input Shift Register (MISR), also known as a linear feedback shift register (LFSR), for both built-in self test (BIST) and the generation of random keys for encryption, which he suggested may be applied to external messages using a form of Rivest-Shamir-Adelman (RSA) encryption. Unfortunately, Butler's encryption approach may require too much computational overhead for encoding and decoding a processor's instructions and data, as may other software-based encryption techniques, such as that described by Horovitz et al. in US Patent Application Publication No. 2013/0067245, published Mar. 14, 2013; and while Henry et al., in US Patent Application Publication No. 2012/0096282, published Apr. 19, 2012, suggest using the XOR operations to decrypt in the “same time” as not decrypting, they still require additional instructions to switch their encryption keys. Therefore, in order to provide an adequate tamper proofing mechanism for cloud computing in multi-processor systems with shared cache memory systems, it may be desirable to employ a pseudo-random key based technique for transparently encoding and decoding instructions and data with minimal overhead, within individual processors, such that protected applications and data may remain encrypted in shared memory spaces.